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Hui Jiang (EE) - Dissertation Defense

Wednesday, February 28, 2018,

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  • Location: ISDE Main Conference Room TN
  • Room: 213 A&B

"Trading off Power Consumption, Speed, and Single-Event Effect Tolerance of CMOS Sequential Logic Circuits in Advanced Technology"

Hui Jiang - Bharat Bhuva, Chair/Adviser of the PhD Committee